`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    21:53:58 02/23/2009 
// Design Name: 
// Module Name:    32_bit_reg 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module bit_reg(clk,dsel,dbus,Aselect,Bselect,abus,bbus);

parameter N=32;

input dsel;
input [N-1:0] dbus;
input clk;
//output [N-1:0] Qi;
input Aselect, Bselect;
output [N-1:0] abus,bbus;
wire [N-1:0] Qi;

DFF X1[N-1 : 0]
(
	.D(dbus),
	.Q(Qi),
	.dsel(dsel),
	.clk(clk)
);

bit_buff A
(
	.sel(Aselect),
	.Qi1(Qi),
	.bus(abus)
);

bit_buff B
(
	.sel(Bselect),
	.Qi1(Qi),
	.bus(bbus)
);
endmodule
